Power consumption in integrated circuits is becoming a significant design criterion since modern chips contain a greater number transistors having increased processing power. Such high-performance transistors leak current, causing static power losses. Further, when such transistors process data, capacitive loads are charged and discharged, causing dynamic power losses or switching power loss. The static power consumption of such circuits tends to increase if no precautions are taken, which is especially important if devices are battery powered. Traditionally, transistor-based, read-only memory (ROM) chips were designed to achieve a tiny area for each memory element in order to generate more memory storage on an integrated circuit chip. Power and performance were sought, but size was the primary design criterion. Presently, there are situations where a larger area memory element may be desirable if power consumption can be reduced without sacrificing performance.
A ROM array is programmed with a combination of ones and zeros during the manufacture of an integrated circuit, and memory cells or bit cells may be arrayed in rows and columns, each bit cell being associated with one row line and one column line. Once a transistor-based, read-only memory (ROM) device has been programmed, the data stored therein is fixed and may be read, but cannot be changed. Prior to reading one or more memory cells in the array, all column lines are typically pre-charged high; that is, a voltage corresponding to a logical 1 is provided to the column lines.
Power consumption may be reduced in traditional ROM designs by: (a) reducing the transistor channel width, increasing transistor channel length, and raising the Vt (threshold voltage) of the transistors to reduce the static current, although at the expense of transistor performance; (b) latching (storing) the output data, gating the clock and shutting off the sense amplifier bias current to eliminate clock switching power and static bias current during inactive periods; this requires chip enable controls; and (c) reducing the sense amplifier bias current to reduce the static power at the expense of the sense amplifier response time (performance). Procedure (a) may be implemented using any transistor architecture. Methods (b) and (c) are not applicable in situations where sense amplifiers are not employed. Disadvantages of these procedures include that the gating clock and bias current require control by an external circuit, thereby adding size, complexity and power consumption.
U.S. Pat. No. 6,363,001 for “ROM With A Reduced Static Consumption,” which issued to Bertrand Borot and Stephane Hanriat on Mar. 26, 2002, and U.S. Pat. No. 6,567,294 for “Low Power Pre-Charge High ROM Array,” which issued to John A. Yochum on May 20, 2003, also address this issue.
FIG. 1 is a schematic representation of two PRIOR ART transistor ROM bit cells, 10, including a pre-charge transistor and a differential sense amplifier for determining the logic output thereof. During fabrication, the NMOS transistor of each bit cell, 12 and 14, may be programmed to output a logical 0 or a logical 1 output, respectively, by having the drain thereof either electrically detached from bit line, 16, or attached thereto, respectively. The content of a bit cell may be read by providing signals to the associated word lines, WLO, 18, or WL1, 20, connected to the gates of the transistors, and measuring the resulting voltage, 22, of bit line 16 using inverting sense amplifier, 24.
Bit line 16 is first pre-charged high by providing a low pre-charge signal, 26, to the gate of PMOS pull-up transistor, 28, which turns on the transistor. Transistor 28 has its source in electrical connection with voltage supply, 30, having a voltage Vdd, and its drain in electrical connection with bit line 16. Transistor 28 is then turned off by providing a high pre-charge signal 26, and bit line 16 remains charged high. It should be mentioned that even if neither transistor in bit cell 12 and bit cell 14 is turned on, there exists a leakage current path between Vdd and lower potential, Vss, supplied by voltage supply, 31, through pre-charge transistor 28 and each transistor (in this case, the transistor in bit cell 14) in electrical contact with bit line 16.
A voltage 18 corresponding to a logical 1 is applied to the gate of the transistor in bit cell 12 for which there is no connection between the transistor and the bit line; therefore, bit line 16 remains charged. If a nonzero reference voltage, 32, is applied to differential sense amplifier 24, a voltage corresponding to a logical 0 will appear at output 22 thereof. A voltage 20 corresponding to a logical 1 is subsequently applied to the gate of the transistor in bit cell 14, having its drain connected to bit line 16 and its source connected to low voltage Vss (which may be at ground potential). The voltage on bit line 16 will be discharged, and differential sense amplifier 24 will generate an output 22 corresponding to a logical 1. Thus, bit cell 12 generates a logical 0 and bit cell 14 generates a logical 1.